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Lab1
Lab2
Video Decoder
Assignment
ECEN 654 Lab.
1. Make a testbench for your state-machine that you coded in the last lab and simulate it.
(Refer to verilog-tutorial1.pdf linked in the lab1 to learn how to write the testbench)
Simulation command:
verilog +gui your_code.v your_testbench.v
2. Make a script file to synthesize your state-machine.
Here are references and an example of the synopsys dc_shell script file.
Lab2.pdf
dc_shell manuals
.synopsys_dc.setup (you should change the file name to .synopsys_dc.setup)
example.tcl
library files
Synthesis command:
dc_shell-xg-t
(or
dc_shell-t
)
dc_shell>
source your_tcl.tcl